To lead technically in ASIC design implementation domain, which may include stages from design architectural understanding till timing signoff for tapeout.
To develop and signoff IC design projects RTL2GDS implementation and flow improvement. Responsibilities include (as applicable)
Architectural and micro-architectural intent understanding
RTL design structure for effective and efficient synthesis implementation
Derive timing constraints from design spec, review and validate with respective designer/architect for signoff
Design‑For‑Test (DFT) implementation, covering basic scan insertion, compression, LOC/LOS, RAMBIST all the way to advanced handling for performance/schedule/coverage trade‑off
Low‑power design; starting from architectural feedback, vector‑driven synthesis/layout optimization and leakage/dynamic power control techniques