SystemC Modeling Engineer

Location: Bengaluru

Experience: 8+ Years

Role Overview

We are seeking an experienced SystemC Modeling Engineer to develop and validate high-performance transaction-level and cycle-accurate models for complex SoCs and IPs. The role requires strong expertise in SystemC, C++, and verification methodologies, with close collaboration across Architecture, RTL, and Design Verification teams.

Key Responsibilities

• Develop and maintain SystemC/TLM-2.0 models for SoC and IP subsystems.
• Build cycle-accurate and transaction-level reference models for architectural exploration and functional validation.
• Drive Model-RTL correlation and debug functional mismatches.
• Collaborate with Architecture, RTL, and DV teams to define modeling requirements and validation strategies.
• Develop validation frameworks, test scenarios, and automated regression flows.