Lead SoC RTL design and implementation for AI chip subsystems.
Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.
Translate architecture and microarchitecture specifications into clean, synthesizable RTL.
Participate in SoC integration, IP integration, bus/interconnect integration, and top-level connectivity.
Work with verification teams to debug simulations, review test plans, and improve coverage.
Work with physical design teams on synthesis, timing closure, area, power, congestion, and ECO issues.
Support FPGA/emulation, silicon bring-up, and post-silicon debugging.
Maintain design documents and mentor junior engineers.