Participate in the development of Physical Design (PD) methodologies across the RTL-to-GDSII flow using industry-standard tools (Cadence, Synopsys, Mentor).
Perform lead level hands-on work in one or more areas including Synthesis, Formal Equivalence, Static Timing Analysis (STA), DRC/LVS/IR/EM Signoff at both module and top level.
Take full ownership of the physical design process at the module level and provide support in top-level integration, collaborating closely with RTL designers, DFT teams, and fabrication partners.
Provide technical mentorship, guiding team members and managing PD team interactions to ensure successful SoC implementation.
Drive PPA optimization, including low-power clock tree design for high-performance systems, and achieve timing closure across multiple corners and use cases.