Development of innovative analog layout ( floor planning, device placement, matching and routing, LVS, DRC, DFM check and reliability verification ) and solving technical issues in different process technologies.
Responsible for layout optimization, post layout extraction and parasitic analysis.
Collaborate with Design Lead, Circuit designers, and Layout engineers to implement custom IPs and archive full chip integration, place and route, top level verification and tape out.
Deliver quality engineering work that meets and exceeds customer expectations all the time
Guide and coach juniors by ensuring their works meets the desired area, performance and power consumption.