Wipro is seeking an engineer in Penang, Malaysia, focusing on full-chip test mode timing signoff and SDC quality checks. The ideal candidate should possess solid Verilog RTL design knowledge and experience, along with a good understanding of synthesis and timing signoff processes.

Your role will include implementing cutting-edge test strategies, supporting automation enhancements, and collaborating with design teams. Strong programming skills and good communication abilities in English and Mandarin are required.