Key Responsibilities

• Design and integrate ARM-based subsystems derived from Arm Corestone reference systems into complex SoCs
• Develop, modify, and integrate RTL (Verilog/SystemVerilog) for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IPs
• Collaborate with architecture teams on micro-architecture updates, feature definition, and performance goals
• Work closely with verification teams to debug functional issues and achieve coverage closure
• Support synthesis, STA, CDC/RDC , and handoff to physical design teams
• Participate in design reviews, documentation, and subsystem bring-up for simulation, emulation, FPGA, and early silicon
• Contribute to methodology improvements for scalable subsystem integration and reuse

Require...