Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers, with OSAT or at internal line.
Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.
Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.
Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).
Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cra...