Position Overview:

We are looking for a highly experienced Senior Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions.

As a Senior Engineer in SoC Design Verification, you will play a key role in leading the SV/UVM based Subsystem and SoC verification strategy, planning, and execution for complex SoC projects. You will collaborate closely with cross-functional teams to ensure the highest quality and performance standards for our SoC products. This role requires deep technical expertise, leadership skills, and a passion for solving challenging verification problems.

Key Responsibilities :

• Architect and develop reusable testbenches and Verification IP (VIP) using SystemVerilog and UVM to create scalable verification environments from scratch.
• Drive