Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
Microarchitecture development and specification.
Ensure that knowledge is shared via great documentation and participation in a culture of collaborative ...