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Senior Design Verification Engineer (eInfochips Inc)

Company

eInfochips, Inc

Location

United States, Minnesota

Type

Full time

Description

:

What You'll Be Doing:

  • Testbenches: Build scalable verification environments using UVM and SystemVerilog.
  • Planning: Create detailed verification plans from architectural specifications.
  • Execution: Write, run, and debug constrained-random tests and directed tests.
  • Coverage: Define, measure, and close functional and code coverage metrics.
  • Gate-Level: Run gate-level simulations to verify power-up and timing states.
  • Automation: Develop scripts to automate regression runs and triage failures.

    • What We Are Looking For:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Languages: Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
  • Methodology: Hands-on experience with UVM (Universal Verification Methodology)
  • Tools: Experience with industry-standard simulators Cadence Xcelium preferred, but...

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