Synthara AG in Zürich is looking for a strong technical leader to own the end-to-end RTL-to-GDSII implementation of complex IP/SoC subsystems. You will be responsible for defining methodologies, leading a team, and ensuring quality metrics are met.This role demands hands-on experience in ASIC physical design, including synthesis and integration of custom designs. A successful candidate will have a strong track record in recruitment and performance development across backend engineering roles. #J-18808-Ljbffr