Overview

RTL/FPGA Design Engineer. Project Duration: 12 Months + chances of further extension. Base pay range CA$110.00/hr - CA$135.00/hr.

Qualifications

• Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering or computer science.
• Experience in front-end ASIC design EDA flows including: Synopsys Design/Fusion Compiler, Synopsys VCS simulation; MBIST, DFT; CDC Lint tools.
• Excellent RTL ASIC/FPGA design skills in Verilog and System Verilog.
• Knowledge of networking standards and wired communications protocols (such as Ethernet).
• Experience with scripting languages such as Python, Perl and TCL.
• Experience with Vivado Design Suite.
• Seniority Level: Mid-Senior level.
• Employment Type: Contract.
• Job Function: Semiconductor Manufacturing.

Top Skills

• ASIC RTL Design
• Clock Domain Crossing (CDC) Analysis