SERDESWORKS PTE. LTD. in Singapore is looking for an RTL / Digital Design Engineer to develop high-speed interface digital subsystems for SerDes and PHY IP. This role involves close collaboration with analog designers and verification engineers.

The ideal candidate should have at least 3 years of experience in digital IC design, strong Verilog skills, and proficiency in RTL simulation tools. Responsibilities include RTL design, verification, and compliance with industry standards.