Define the overall 3D-NAND memory architecture, including array organization (Plane/Bank/Page/Block structure), word line/bit line layout, shared resource strategies, etc.
Lead architecture feasibility studies, technical risk assessments, and roadmap planning, promoting IP reuse, scalability design, and future technology node evolution.
Design and optimize erase/read algorithms, balancing speed, endurance, data retention, and interference management (such as read disturbances and program disturbances).
Develop ECC (Error Correction Code) strategies and integration solutions, evaluating the impact of BCH, LDPC (hardware decoding/software decoding), and other solutions on area, latency, power consumption, and error correction capabilities.
Define page and block management level logic, supporting advanced functions such as copy-back, multi-plane operation, suspend/resume, and background erase.