• Define system-level power management architecture and operating modes
• Define CPU and cluster power states and their coordination mechanisms
• Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions
• Define PM policies, sequencing, and state transitions across the platform
• Define hardware–firmware power management interfaces and compliance expectations
• Define power management requirements and constraints to guide implementation teams
• Align architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategy
• Support silicon bring-up and post-silicon power behavior validation

Required Experience

• 7+ years in SoC or CPU power management architecture
• Direct experience with ARM CPU power management architecture, including familiarity with ARM power management specifications and compliance requirements (e.g.,...