Physical Design Lead, Static Timing Analysis

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

**Advanced**

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
+ Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
+ Experience analyzing cross-chip clock distribution networks.
+ Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC).
+ Experience using tool command language (Tcl) commands for timing analysis...