We are seeking a highly motivated Mixed-Signal Verification Engineer to support verification of analog and mixed-signal IP integrated within digital-on-top SoC environments. Reporting to the Analog Design Team Manager, this individual contributor role will lead development and execution of verification strategies for complex power, clocking, and mixed-signal subsystems prior to tape-out. The ideal candidate brings strong expertise in SystemVerilog, UVM methodologies, and behavioral modeling, along with hands-on experience verifying analog IP in large-scale SoC environments.
Key Responsibilities