Architect, design and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial and edge computing markets. Responsible for micro-architecture, Verilog RTL implementation, logic synthesis and timing closure. Perform trade-off analysis on performance, area and complexity. Ensure front-end to back-end handoff IP quality checks such as Lint/CDC/Synthesis/STA/LEC. Provide technical support to the engineering IP team, including code reviews, and assist in project planning and tracking. Work closely with IP design verification engineers and with marketing and application engineering to define feature requirements and resolve customer issues.