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Lead Silicon Yield & Debug Engineer

Company

UST Malaysia

Location

, penang, malaysia, penang

Type

Full-time

UST Malaysia is seeking a qualified individual to lead the development and execution of characterization plans, analyze complex electrical behaviors, and drive root-cause investigations. Preferred candidates will have extensive silicon bring-up experience, proven yield analysis expertise, and strong backgrounds in data automation. You'll collaborate with cross-functional teams and mentor junior engineers in methodologies and best practices, all while contributing to the improvement of testing and yield outcomes.
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