Role Overview

• Design Verification Engineer with expertise in System Verilog, UVM methodology.
• Experience in ASIC-Memory Design methodology.
• DDR protocol knowledge is preferable.
• This engineer shall collaborate with architects and designers to meet performance and reliability requirements.
• Mixed signal verification.

Must Have

• Master’s degree in Electrical Engineering, Computer Engineering.
• 5+ years of experience in ASIC/DRAM/NAND/NOR Memory design verification
• Strong skills in SystemVerilog and UVM methodology.
• Cadence tool chain knowledge (Virtuoso, ADE, Xcelium, Simvision) or equivalent Synopsys verification tool chain.
• Problem Solving and Communication skills.

Responsibilities

• Develop and maintain UVM-based verification environments.
• Create test plans, testbench and stimuli.
• Create ...