Eximietas is Hiring – Senior PLL Design Engineers/Leads/Architects. Experience: Min 10+ Years Locations: Bengaluru, India About the Role: Qualifications: Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering. Minimum 10+ years of experience in PLL Design. Roles & Responsibilities: Architect, design and development of LC PLL Circuits. Strong knowledge and fundamentals of clocking circuits, CDR and SERDES designs. Good hands on experience in high speed circuits for 32G, 64G and higher. Working experience in Samsung PDK lower technology nodes will be an added advantage. Interested candidates, please share your resumes: Referrals are highly appreciated....!