Hi,

Opening for DV with ARM.

PREFERRED EXPERENCE:

- ASIC design verification experience of 3-5 years.

- Understanding or technical expertise in functional verification of microprocessor designs.

- Experience with Verilog/System Verilog HDL, programming in Perl/Python/Ruby, C/C++, Makefile and logic simulation.

- Experience with x86, ARM or any other industry standard microprocessor architecture.

- Strong understanding of computer architecture and assembly programming, preferably x86.

- Strong understanding the design and verification life cycle.

- Experience in CPU cache/memory subsystem verification is a plus

- Simulation and debugging with a Verilog based functional simulator.

- Strong problem-solving and debugging skills in both pre- and post-silicon environments.

- Exposure to leadership or mentorship is an asset.

- Familiarity with us...