At Arm, the High-Speed I/O Architect defines and designs innovative on-chip interconnect architectures-coherent and non-coherent-for scalable SoC platforms. You will work across markets including mobile, automotive, datacenter, networking, and IoT, contributing to production-quality silicon with top-tier performance and efficiency. Architect high-speed interconnect subsystems—including PCIe, CXL, and UA Link—and define coherent and non-coherent communication architectures across a range of silicon products.

Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in close partnership with SoC architecture and core technology teams.

Lead early architecture engagements with customers, shaping system requirements and delivering clear, implementation-ready specifications.

Collaborate with performance, power, and physical design teams to optimize PCIe/CXL/UA Link subsystem behavior, bandwidth, latency, and overall system efficiency.

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